#ifndef __EXYNOS4412_REG_CLK_H__
#define __EXYNOS4412_REG_CLK_H__

#define EXYNOS4412_CLK_BASE				(0x10030000)

#define CLK_SRC_LEFTBUS					(0x04200)
#define CLK_MUX_STAT_LEFTBUS			(0x04400)
#define CLK_DIV_LEFTBUS					(0x04500)
#define CLK_DIV_STAT_LEFTBUS			(0x04600)
#define CLK_GATE_IP_LEFTBUS 			(0x04800)
#define CLK_GATE_IP_IMAGE 				(0x04930)
#define CLKOUT_CMU_LEFTBUS 				(0x04a00)
#define CLKOUT_CMU_LEFTBUS_DIV_STAT		(0x04a04)
#define CLK_SRC_RIGHTBUS				(0x08200)
#define CLK_MUX_STAT_RIGHTBUS			(0x08400)
#define CLK_DIV_RIGHTBUS				(0x08500)
#define CLK_DIV_STAT_RIGHTBUS			(0x08600)
#define CLK_GATE_IP_RIGHTBUS 			(0x08800)
#define CLK_GATE_IP_PERIR 				(0x08960)
#define CLKOUT_CMU_RIGHTBUS 			(0x08a00)
#define CLKOUT_CMU_RIGHTBUS_DIV_STAT	(0x08a04)
#define EPLL_LOCK						(0x0c010)
#define VPLL_LOCK						(0x0c020)
#define EPLL_CON0						(0x0c110)
#define EPLL_CON1						(0x0c114)
#define EPLL_CON2						(0x0c118)
#define VPLL_CON0						(0x0c120)
#define VPLL_CON1						(0x0c124)
#define VPLL_CON2						(0x0c128)
#define CLK_SRC_TOP0					(0x0c210)
#define CLK_SRC_TOP1					(0x0c214)
#define CLK_SRC_CAM0					(0x0c220)
#define CLK_SRC_TV						(0x0c224)
#define CLK_SRC_MFC						(0x0c228)
#define CLK_SRC_G3D						(0x0c22c)
#define CLK_SRC_LCD						(0x0c234)
#define CLK_SRC_ISP						(0x0c238)
#define CLK_SRC_MAUDIO					(0x0c23c)
#define CLK_SRC_FSYS					(0x0c240)
#define CLK_SRC_PERIL0					(0x0c250)
#define CLK_SRC_PERIL1					(0x0c254)
#define CLK_SRC_CAM1					(0x0c258)
#define CLK_SRC_MASK_CAM0				(0x0c320)
#define CLK_SRC_MASK_TV					(0x0c324)
#define CLK_SRC_MASK_LCD				(0x0c334)
#define CLK_SRC_MASK_ISP				(0x0c338)
#define CLK_SRC_MASK_MAUDIO				(0x0c33c)
#define CLK_SRC_MASK_FSYS				(0x0c340)
#define CLK_SRC_MASK_PERIL0				(0x0c350)
#define CLK_SRC_MASK_PERIL1				(0x0c354)
#define CLK_SRC_MUX_STAT_TOP0			(0x0c410)
#define CLK_SRC_MUX_STAT_TOP1			(0x0c414)
#define CLK_SRC_MUX_STAT_MFC			(0x0c428)
#define CLK_SRC_MUX_STAT_G3D			(0x0c42c)
#define CLK_SRC_MUX_STAT_CAM1			(0x0c458)
#define CLK_DIV_TOP						(0x0c510)
#define CLK_DIV_CAM0					(0x0c520)
#define CLK_DIV_TV						(0x0c524)
#define CLK_DIV_MFC						(0x0c528)
#define CLK_DIV_G3D						(0x0c52c)
#define CLK_DIV_LCD						(0x0c534)
#define CLK_DIV_ISP						(0x0c538)
#define CLK_DIV_MAUDIO					(0x0c53c)
#define CLK_DIV_FSYS0					(0x0c540)
#define CLK_DIV_FSYS1					(0x0c544)
#define CLK_DIV_FSYS2					(0x0c548)
#define CLK_DIV_FSYS3					(0x0c54c)
#define CLK_DIV_PERIL0					(0x0c550)
#define CLK_DIV_PERIL1					(0x0c554)
#define CLK_DIV_PERIL2					(0x0c558)
#define CLK_DIV_PERIL3					(0x0c55c)
#define CLK_DIV_PERIL4					(0x0c560)
#define CLK_DIV_PERIL5					(0x0c564)
#define CLK_DIV_CAM1					(0x0c568)
#define CLKDIV2_RATIO					(0x0c580)
#define CLK_DIV_STAT_TOP				(0x0c610)
#define CLK_DIV_STAT_CAM0				(0x0c620)
#define CLK_DIV_STAT_TV					(0x0c624)
#define CLK_DIV_STAT_MFC				(0x0c628)
#define CLK_DIV_STAT_G3D				(0x0c62C)
#define CLK_DIV_STAT_LCD				(0x0c634)
#define CLK_DIV_STAT_ISP				(0x0c638)
#define CLK_DIV_STAT_MAUDIO				(0x0c63c)
#define CLK_DIV_STAT_FSYS0				(0x0c640)
#define CLK_DIV_STAT_FSYS1				(0x0c644)
#define CLK_DIV_STAT_FSYS2				(0x0c648)
#define CLK_DIV_STAT_FSYS3				(0x0c64c)
#define CLK_DIV_STAT_PERIL0				(0x0c650)
#define CLK_DIV_STAT_PERIL1				(0x0c654)
#define CLK_DIV_STAT_PERIL2				(0x0c658)
#define CLK_DIV_STAT_PERIL3				(0x0c65c)
#define CLK_DIV_STAT_PERIL4				(0x0c660)
#define CLK_DIV_STAT_PERIL5				(0x0c664)
#define CLK_DIV_STAT_CAM1				(0x0c668)
#define CLKDIV2_STAT					(0x0c680)
#define CLK_GATE_BUS_FSYS1				(0x0c744)
#define CLK_GATE_IP_CAM					(0x0c920)
#define CLK_GATE_IP_TV					(0x0c924)
#define CLK_GATE_IP_MFC					(0x0c928)
#define CLK_GATE_IP_G3D					(0x0c92c)
#define CLK_GATE_IP_LCD					(0x0c934)
#define CLK_GATE_IP_ISP					(0x0c938)
#define CLK_GATE_IP_FSYS				(0x0c940)
#define CLK_GATE_IP_GPS					(0x0c94c)
#define CLK_GATE_IP_PERIL				(0x0c950)
#define CLK_GATE_IP_BLOCK				(0x0c970)
#define CLKOUT_CMU_TOP					(0x0ca00)
#define CLKOUT_CMU_TOP_DIV_STAT			(0x0ca04)

#define MPLL_LOCK						(0x10008)
#define MPLL_CON0						(0x10108)
#define MPLL_CON1						(0x1010c)
#define CLK_SRC_DMC						(0x10200)
#define CLK_SRC_MASK_DMC				(0x10300)
#define CLK_SRC_MUX_STAT_DMC			(0x10400)
#define CLK_DIV_DMC0					(0x10500)
#define CLK_DIV_DMC1					(0x10504)
#define CLK_DIV_STAT_DMC0				(0x10600)
#define CLK_DIV_STAT_DMC1				(0x10604)
#define CLK_DIV_BUS_DMC0				(0x10700)
#define CLK_DIV_BUS_DMC1				(0x10704)
#define CLK_DIV_IP_DMC0					(0x10900)
#define CLK_DIV_IP_DMC1					(0x10904)
#define CLKOUT_CMU_DMC					(0x10a00)
#define CLKOUT_CMU_DMC_DIV_STAT			(0x10a04)
#define DCGIDX_MAP0						(0x11000)
#define DCGIDX_MAP1						(0x11004)
#define DCGIDX_MAP2						(0x11008)
#define DCGPERF_MAP0					(0x11020)
#define DCGPERF_MAP1					(0x11024)
#define DVCIDX_MAP						(0x11040)
#define FREQ_CPU						(0x11060)
#define FREQ_DPM						(0x11064)
#define DVSEMCLK_EN						(0x11080)
#define MAXPERF							(0x11084)
#define DMC_PAUSE_CTRL					(0x11094)
#define DDRPHY_LOCK_CTRL				(0x11098)
#define C2C_STATE						(0x1109c)
#define APLL_LOCK						(0x14000)
#define APLL_CON0						(0x14100)
#define APLL_CON1						(0x14104)
#define CLK_SRC_CPU						(0x14200)
#define CLK_SRC_MUX_STAT_CPU			(0x14400)
#define CLK_DIV_CPU0					(0x14500)
#define CLK_DIV_CPU1					(0x14504)
#define CLK_DIV_STAT_CPU0				(0x14600)
#define CLK_DIV_STAT_CPU1				(0x14604)
#define CLK_GATE_IP_CPU					(0x14900)
#define CLKOUT_CMU_CPU					(0x14a00)
#define CLKOUT_CMU_CPU_DIV_STAT			(0x14a04)
#define ARMCLK_STOPCTRL					(0x15000)
#define ATCLK_STOPCTRL					(0x15004)
#define PWR_CTRL						(0x15020)
#define PWR_CTRL2						(0x15024)
#define L2_STATUS						(0x15400)
#define CPU_STATUS						(0x15410)
#define PTM_STATUS						(0x15420)
#define CLK_DIV_ISP0					(0x18300)
#define CLK_DIV_ISP1					(0x18304)
#define CLK_DIV_STAT_ISP0				(0x18400)
#define CLK_DIV_STAT_ISP1				(0x18404)
#define CLK_GATE_IP_ISP0				(0x18800)
#define CLK_GATE_IP_ISP1				(0x18804)
#define CLKOUT_CMU_ISP					(0x18a00)
#define CLKOUT_CMU_ISP_DIV_STAT			(0x18a04)
#define CMU_ISP_SPARE0					(0x18b00)
#define CMU_ISP_SPARE1					(0x18b04)
#define CMU_ISP_SPARE2					(0x18b08)
#define CMU_ISP_SPARE3					(0x18b0c)

#endif /* __EXYNOS4412_REG_CLK_H__ */
